1. Field of the Invention
The invention relates in general to a structure and a fabrication method of an electrostatic discharge protection circuit. More particularly, the invention relates to a structure and a fabrication method of an electrostatic discharge protection circuit, in which a sinker layer and a buried layer are formed to provide a low resistant current path.
2. Description of the Related Art
The electrostatic discharge is an electrostatic drift phenomenon from a surface of a non-conductor that damages semiconductors or other circuit components in an integrated circuit. For example, hundreds to thousands of volts of static electricity carried by a human body walking on a blanket under a higher relative humidity can be detected. When the relative humidity is lower, more than ten thousand volts of electrostatic voltage can be detected. The equipment for packaging or testing integrated circuits also generates hundreds to thousands of volts of static electricity. When brought into contact with the above charge carriers (human body, equipment or instrument), the chips are discharged thereto. The surge caused by such electrostatic discharge may damage the integrated circuit of the chip or even cause failure of the integrated circuit.
To prevent damage to the integrated circuit of the chip, various mechanisms to suppress the electrostatic discharge have been proposed. Most commonly, hardware prevention is applied by forming an on-chip electrostatic discharge protection circuit between the internal circuit and each pad thereof.
FIG. 1 shows a schematic structure of a conventional NMOS electrostatic discharge protection circuit.
Referring to FIG. 1, a P well 102 is formed in a P-type substrate 100, and an NMOS transistor 104 and a P+ substrate-connecting region 114 are formed in the P well 102.
The above NMOS transistor 104 comprises a gate 106, a source 108, and a drain 110. The P+ substrate-connecting region 114 is isolated from the NMOS transistor 104 by a shallow trench isolation layer 112.
A guard ring 118 is formed on the substrate 100 surrounding the P+ substrate-connecting region 114. For the NMOS transistor 104, the guard ring 118 includes an N+ doped region with a conductive type opposite to that of the P well 102. The guard ring 118 and the P+ substrate-connecting region 114 are isolated from each other by a shallow trench isolation layer 116.
Referring to FIG. 2, the resistance of the substrate 100 is decreased as the voltage applied to the drain 110 is increased. When the voltage exceeds Vt1, the resistance of the substrate 100 is reduced sufficiently to switch on the PN junction near the source 108. Meanwhile, the parasitic bipolar transistor is activated to generate a snapback voltage. Such snapback voltage rapidly drops to voltage VSb and simultaneously conducts the electrostatic discharge current.
However, the flow path of the electrostatic discharge current is normally along a surface of the gate dielectric layer. When such current is large, the thermal energy generated thereby is concentrated near the flow path, that is, near the surface of the gate dielectric layer. A large thermal energy may blow the gate dielectric to cause failure of the electrostatic discharge protection circuit.